1. Field of the Invention
The present invention relates to a semiconductor memory device and its fabricating method and more particularly, to a contact forming method in a MOSFET or a DRAM.
2. Description of the Related Art
Recently, a MOS type DRAM has made remarkable progress in its high integration and large capacity with the advancement of semiconductor techniques, in particular, fine processing techniques.
However, the high memory integration has a problem that the area of a capacitor for storing data (charges) is decreased and this results in erroneous reading operation of the memory contents or in the generation of a soft error caused by the destruction of the memory contents due to .alpha. rays or the like.
For the purpose of solving such a problem and realizing the higher integration and increased capacity, there has been suggested a laminated memory cell structure, in which a MOS capacitor is formed on a memory cell region and one electrode of the capacitor is electrically connected to one electrode of a switching transistor formed on a semiconductor substrate to enlarge an area for the MOS capacitor and thereby to substantially increase the electrostatic capacitance of the MOS capacitor.
Such a laminated memory cell is shown in FIGS. 55(a) to 55(c). More in detail, one memory cell region is provided by isolating a p-type silicon substrate 101 with an insulating film 102 for element isolation. In the memory cell region, a gate electrode 106 is formed between adjacent source and drain regions 104a and 104b of an n-type diffusion layer with a gate insulating film 105 disposed between the gate electrode 106 and source and drain regions 104a and 104b, thereby forming a MOSFET as a switching transistor. Further formed on the MOSFET is a first capacitor electrode 110. The first capacitor electrode 110 is contacted through its storage node contact hole 108 provided in an insulating film 107, with the source region 104a of the MOSFET, and covers the gate electrode 106 of the MOSFET and a gate electrode (word line) of an adjacent MOSFET. A capacitor insulating film 111 and a second capacitor electrode 112 are sequentially laminated on the first capacitor electrode 110 to thereby form a capacitor. The laminated memory cell is fabricated in the following manner.
That is, in the laminated memory cell, source/drain regions 104a and 104b of the n-type diffusion layer are formed in a p-type silicon substrate 101 and each of gate electrodes 106 is formed between the source/drain regions 104a and 104b through a gate insulating film 105, whereby an MOSFET is formed as a switching transistor.
Next, a silicon oxide film as an insulating film 107 is formed all over the substrate 101 and then a storage node contact hole 108 for contact with the drain region 104a is formed to thereby form a pattern of a first capacitor electrode 110 made of a heavily doped polycrystalline silicon layer.
Subsequently, on the first capacitor electrode 110, a capacitor insulating film 111 of silicon oxide or the like and a second polycrystalline silicon layer 112 are sequentially deposited.
After this, the polycrystalline silicon layer 112 is in subjection to an ion implantation of such ions as phosphorus and then subjected to a heat treatment of some 900.degree. C. and 120 minutes to form a heavily-doped polycrystalline silicon layer having a desired conductivity.
And the highly-doped polycrystalline silicon layer is subjected to a patterning process to obtain an MOS capacitor having a capacitor insulating film 111 sandwiched by the second capacitor electrode 112 and the first capacitor electrode 110.
Finally, on the thus formed polycrystalline silicon layer, an inter-layer insulating film 107' is formed, and therein a bit line contact hole 113 is made. Further, a bit line made of molybdenum polycide or the like is formed in the bit line contact hole 113, on which an inter-layer insulating film 107" is formed to obtain a memory cell comprising a MOSFET and a MOS capacitor.
With such a structure, the storage node electrode can be extended up to a position above the element isolation region and the step difference of the storage electrode can be utilized, whereby the capacitance of the capacitor can be increased several to several ten times than that of a planar structure type.
A DRAM of such a laminated memory cell structure type, however, has the following disadvantage. As the memory integration is advanced, a distance (shown by l 1 in FIG. 55(a)) between the storage node contact hole and gate electrode as well as a distance (shown by l 2 in FIG. 55(b)) between the bit line contact hole and gate electrode must be shortened. This results in that a short-circuiting tends to occur between the storage node and the gate electrode and between the bit line and the gate electrode and thus the reliability is reduced.
Further, as the memory integration is advanced, it becomes more difficult to secure a large capacitance of the capacitor.
Even when the storage node electrode is extended up to a position above the element isolation zone, the area of flat part of the storage node electrode is still very small. When the storage node electrode is made thicker to utilize the side portion, the step difference of the storage electrode is increased, and therefore when the bit line contact hole is made in the upper layer of the capacitor, the over-etching time becomes long because distance from the upper layer and the substrate is long, thus resulting in possible reduction in the reliability.
In addition, as the memory integration is advanced, distance between the conductive layers in the contact hole becomes remarkable small with the result that the conductive layers may be short-circuited through the inter-layer insulating film 107. It will be appreciated that since the inter-layer insulating film is subjected to an etching process during formation of the contact hole, the film is deteriorated, which is a major cause of such short-circuiting.